Typical computing systems include one or more processors and one or more memories coupled thereto. System memory is often formed of dynamic random access memory (DRAM). Memory access to a DRAM can be a high bottleneck in such systems. The DRAM memory access latency is high due to DRAM memory organization. In order to access a piece of data from DRAM, bitlines are first precharged to a certain voltage level. An activate command is then issued to sense data stored in a row and hold it in sense amplifier/row buffer circuitry. The sense amplifier performs the role of sensing the charge stored in DRAM capacitive bitcells, amplifying it and then holding it. This process is called row activation. Subsequent requests to the same row (row buffer hits) can be served from the sense amplifiers and do not encounter precharge and activation latencies. Before another access to a different row (row buffer miss) can be served, the bitlines are again precharged. Delaying this precharge until another activate command to a different row arrives enables more row buffer hits. However, these row buffer hits come at the cost of delaying the incoming activation until the precharge completes. On the other hand, precharging immediately after an access to a row is completed avoids delaying future activations, but compromises row buffer locality.
Memory controllers trade off between these two extremes by holding idle rows open for a certain time after the last request to a row is seen or until the next activation, whichever comes earlier. Despite employing such a policy, inefficiencies still exist.